As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option available to users is information handling systems. An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.
An information handling system may use a myriad of various internal communications buses, such as one or more I2C buses, to communicate data or instructions between information handling resources of the information handling system. In some cases, a plurality of “master” devices may be coupled to a bus, wherein such master devices may each be configured to perform input/output (I/O) operations with one or more “target” devices via the bus. In order that only one master device performs I/O at a given time, standards for some bus technologies may provide for an arbitration mechanism among master devices. However, some bus standards have disadvantages.
For example, in the I2C standard, native I2C arbitration procedures may not be sufficient when communicating with target devices, such as electrically erasable programmable read-only memories (EEPROMs) or other paged target devices. To illustrate, EEPROMs, other memory devices, or other target devices may support a maximum page size for a write operation which is coupled with a delay to allow the target device to commit the write operation. After such paged write operation, the master device may issue a stop condition before a complete write of all pages of the data to be written, which may open the I2C bus up to another arbitration process among master devices. Thus, because a write operation may take multiple I2C transactions to complete, other masters may access the bus prior to completion of the entire write operation, which can lead to undesirable conditions or results, such as data corruption that could occur due to a read occurring prior to all pages of a write operation being written to a target device.
This problem has long existed, particularly in I2C communication, and there has been a long-felt need for a solution which does not require a complicated software scheme in order to address the problem.